If chips can be packaged more densely on the surface of the silicon circuit board, the dimensions and cost of the module can be reduced and system performance improved. One possible method of maximizing packaging densities involves placing chips atop one another to form three-dimensional stacks referred to as stacked-chip devices or stacked-die devices. Over the past several years there has been some interest in stacking chips where possible. Such chip-stacking schemes include stacking a number of decreasing sized chips in order to facilitate the wire-bonds or stacking a number of same-sized chips using spacers, or employing a beveling technique or using “T-cut” dies for the upper dies. As the trend moves toward stacking more die, from 2–4 stacked die, in typical devices today, to 6–8 stacked die in the near future, and more, problems arise.
For example, for a decreasing sized die scheme, eventually a point is reached where the size of the upper die is ineffective. For beveled or T-cut die schemes there is a limit on the difference in size between the lower and upper die in a stack (i.e., excessive overhang is more difficult to process and leads to less stable stacked-die devices.
Moreover, each of these schemes presents the problem of increased yield losses. As the number of stacked dies increases, the yield loss increases. The stacked-die device is not completely tested until it is complete. Temperature and other tolerance testing can be completed on individual dies at the die level, pre-stacking, but such testing is not indicative of overall functionality for the stacked-die device. Especially in cases where one of the stacked dies implements a logic processor device, testing at speed is not reliable prior to all of the electrical connections of the entire device being completed.
To address the problems of stack limitations and yield loss, the concept of sub-packaging of stacked dies has been introduced. In such a scheme, multiple sub-packages, each comprising a stacked-die device, are produced and tested. Upon successful testing, two or more sub-packages are stacked and electrically connected to form a stacked-die device.
FIG. 1 illustrates a stacked-die device comprised of stacked sub-packages in accordance with the prior art. Stacked-die device 100, shown in FIG. 1 includes three sub-packages 105a, 105b and 105c, which may be stacked-die packages such as packages 105b and 105c. Package 105a includes a substrate 110a with conductive balls 120 (e.g., ball grid array (BGA)) formed on the lower surface 111 of the substrate 110a. The conductive balls 120 are for electrically connecting the substrate 110a to a motherboard (not shown). A die 130a is disposed upon the upper surface 112 of the substrate 110a. 
Package 105b comprises a stacked-die device having die 130c stacked atop die 130b. Package 105c comprises a stacked-die device having dies 130d–130f stacked one atop the other as shown. All of the dies, 130a, 130b and 130c, and 130d–130f are electrically connected to respective substrates 110a–110c or to one another with wire-bonds 140. The wire-bonds 140 for each sub-package are typically covered with a molding compound 145 for protection prior to stacking the sub-packages. The sub-packages are electrically connected to each other with interconnections 150, which may be copper joints between the sub-packages.
The stacked-die device 100 addresses some of the disadvantages of stack limitations and yield loss, but has disadvantages as well. For example, the copper implants that form the connecting joints between sub-packages require additional space. That is, the interconnections 150 between sub-packages have to be somewhat removed from the wire-bonds 140 so that they are not covered by the molding compound 145. This increases the size of the stacked-die device. Also, forming the copper implants requires additional processes (e.g., drilling), which increase the cost and practically limit the configuration of each package to a standard shape and size. FIG. 1A is a top-down view of a sub-package for the stacked-die device 100 described above in reference to FIG. 1. As shown in FIG. 1A, the copper implants 150 used to connect sub-packages have a carrier 155. The carrier is beyond the area on the substrate 110a in which wire-bonds 140 may be placed. For a given size, die 130a, the substrate 110a and hence the sub-package 105a need to be large enough to accommodate the carrier 155.